Paper Title
Metal Shared Memory Interconnects – MSMI
Abstract
The TCP/IP protocol was deployed in 1983 and has not had an upgrade to keep pace with the increase in packet
volume and trunk speed that today’s applications require. In this paper authors propose a new protocol – Metal Shared
Memory Interconnects (MSMI) algorithm and its design, which address all the above TCP problems and leverages the new
multi-core processor technologies and also new protocol architecture on dual system to make networks intelligent. Such
novel protocol makes use of the many cores architecture on FPGA’s and metal algorithms to create many deeply dense
pipelines working on hundreds of cores interconnected to their memory that are built on FPGA’s to transfer payloads of the
speeds from 10Gbps, 120Gbps and above. For e.g. this new protocol not only reaches transfer rates 9.5Gbps on 10Gbps but
also makes the networks intelligent and can achieve 95-99% bandwidth utilization. All TCP flows within a trunk circuit
accelerated to the maximum rates. As circuits are upgraded from existing 10Gbps to 100Gbps and above they work together
to permit the utilization increase, lost packet elimination, and TCP speed gains across a whole network. The gateways built
on this new protocol can be added incrementally to existing networks and the proposed protocol is compatible and
transparent to existing traffic and protocols. First time in the history of communications in the lab and also on the live circuit
of 2000miles we have successfully tested on 10Gbps line and achieved stateful transfer rates reaching 3.3Gbps with heavy
losses induced both input side and output side of the trunk. The metal algorithms and the software is developed by creating
reconfigurable FPGA cores (64) on Xilinx FPGA vertex 7, by creating 16 pipelines 8 in each direction.
Index Terms- MSMI, FPGA, Multi-Core, Low Latency, HPEC, HPC