Design Of A Low Power Current Mirror Ota For Two-Step Incremental Sigma-Delta Adc
This paper presents an improved method for design of CMOS low power class-AB operational transconductance
amplifier (OTA) for two- step incremental Sigma-Delta ADC. Authors have used current mirror topology with rail-to-rail
output swing and also used gain enhancement architecture in the proposed design. The design is simulated in 0.18µm UMC
CMOS technology with supply voltage is 1.8V. Simulation results are obtained with and without load capacitor and achieved
improved results as compared to the earlier published work are: DC gain 73.81dB,GBW 53.15MHz andthe static power
consumption is about 10.296µW. This work will be beneficial for the young researchers, designers and manufacturers.
Keywords- Current Mirror, Class-AB Operational Trans-conductance Amplifier (OTA), Gain Enhancement.