Signal Transmission Performance of TSV Stacked Die
3-D integration technologies have been of increasing interest for compact and high performance system
integration and packaging. Through-silicon-via (TSV) is one of the key technologies to enable vertical connections for
stacked ICs and silicon packages. A TSV is a conducting copper nail, which provides an electrical connection though the
substrate and is expected to be used extensively to provide high-speed interconnects between the top and bottom of the
active dies. High speed signals on TSVs can interact with the active device area through a lossy substrate, causing circuit
malfunctioning and signal integrity problems. This paper evaluates the effects of substrate conductivity on the electrical
performance of 3D stacked die structures based on High Frequency Structure Simulator (HFSS) techniques. The results
indicate the loss term is determined by the conductance of the silicon substrate. Thus, the high-resistivity material as the
substrate can reduce the insertion loss of not only a TSV but also a horizontal interconnect on the substrate.
Keywords- 3D Stacked-ICs, Through Silicon Via (TSV), High Frequency Structure Simulator (HFSS).