Paper Title :Verification of Ethernet Protocol

Author :Shivleela G. Wadle, Sanjaykumar K. Parchandekar

Article Citation :Shivleela G. Wadle ,Sanjaykumar K. Parchandekar , (2016 ) " Verification of Ethernet Protocol " , International Journal of Advance Computational Engineering and Networking (IJACEN) , pp. 1-3, Volume-4, Issue-8

Abstract : Verification is the most important aspect of a design. An effective approach that requires less time is the need of the hour. There is a need to facilitate re use and randomize tests to save time and increase quality of testing. The Ethernet physical layer devices deal with the raw hardware and the higher level layers like MAC through Physical media attachment and media independent interface. Hence, there is a need for a robust automated verification process that can help in all kinds of traffic that the device can handle in all possible random ways. This paper describes the use of SystemVerilog as a language and UVM on top of it to facilitate a comprehensive verification supporting re use of code and the use of golden IP models. The entire test environment is created in UVM to achieve the above set goals. Index Terms— UVM(universal verification methodology), SV(SystemVerilog), DUT(Design Under Testing)

Type : Research paper

Published : Volume-4, Issue-8

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